Dates
25 - 29 September 2017
Venue
University of Zagreb, Faculty of Electrical Engineering and Computing
Unska 3, HR-10000 Zagreb, Croatia
Room A110
Contact
Professor Vedran Bilas
Registration
Registration for the Cadence Academic Workshop is FREE and MUST be made by completing the REGISTRATION FORM. Number of participants is limited and the registration will be confirmed by an email on a first-come, first-served basis.
Registration deadline is 20 September 2017.
Cadence Academic Workshop Outline
Custom IC Design Using the Virtuoso Platform
The course will cover the full design flow with Cadence Design Systems Virtuoso platform staring form Schematic capture, building simulation testbenches and running simulations with Analog Design Environment and Spectre simulator all the way to constraint and connectivity driven layout design and layout signoff verification. Basics of mixed signal simulation with AMS Designer and parasitic extraction with Quantus QRC will also be introduced. The course emphasis is on hands on lab work.
Workshop Programme
Introduction to Virtuoso platform
- Working with libraries
Schematic Entry with Virtuoso Schematic Editor
- Creating schematic designs
- Creating schematic symbols
- Creating design configurations
Analog Simulation using Virtuoso Analog Design Environment Explorer
- Creating testbenches
- Setting up analog simulation
- Using Spectre and APS circuit simulators
- Analyzing simulation results
Design Centering with ADE Assembler
- Using multiple testbenhces
- Extensive design analysis over process and corners
Introduction Mixed Signal Simulation with AMS Designer
- Setting up and running Mixed signal simulations in ADE
Virtuoso Layout Suite
- Introduction to Virtuoso Layout suite
- Connectivity and constraint driven layout
- Interactive and automated routing
- DRC and LVS with Cadence PVS
- Parasitic extraction and resimulation